Repeatable FPGA-on-board optimization: simply recreating the PCB information adds steps, but little else.

Author:Smetana, Frank
Position:DESIGNER'S NOTEBOOK
 
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ASSIGNING I/O PINS has transgressed well beyond a sketch or spreadsheet, and routing these large devices requires collaboration between FPGA and PCB designers. With modern I/O routing tools, savings can be realized in layer count, trace length (and consequential signal integrity improvement), and via use.

A good starting point is automation of symbol creation and PCB schematic connectivity to streamline the FPGA pin assignment process. Designers need to proceed with caution and investigate how such automation tools affect the complete product design flow. For example, an approximate recreation of the PCB information for use by an FPGA I/O assignment tool simply adds another step and another representation of the data--without fostering design convergence. Tools that create a unique set of product-specific symbol fractures for each FPGA design should be weighed against the company's reuse and library management goals. Recreation of an entire local symbol and schematic set with each iterated pin change can make design a data management nightmare.

Instead, an FPGA/PCB optimization process that is the same from project-to-project focuses on a centralized library structure that promotes common practices among designs, as well as design reuse. Setting up this corporate "generic" environment that creates a true FPGA/PCB symbol theme has many downstream benefits, and also allows pin reassignments to be instantly communicated in a "pushbutton" fashion to all members of the design team.

At the librarian level, initially all symbol fractures for an FPGA are automatically generated, tied to the physical cell and part number, installed into a centralized library, approved, and made available for all users of the FPGA. FPGA power, ground, and config pins essential to the FPGA are optimally defined by the librarian, allowing functional designers to focus efforts on optimizing the I/O pins specific to the design. This approach not only fosters reuse, but avoids further design-specific regeneration of the symbol set for each iteration.

The upfront library configuration pays off not only in reusability, but also the ease through which pin iteration steps are completed. When a pin assignment change is made to the FPGA in the board context through the FPGA optimization tool, schematics containing the symbol set for the FPGA are updated with new connectivity information, and the...

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