Pin-pitch under 0.8 mm: fine-pitch BGAs dramatically increase in pin count and will drive adoption of HDI.

Author:Pfeil, Charles
Position:BGA BULLETIN

THE PREVIOUS ARTICLES have focused primarily on fanout and routing of large (over 1500 pins) BGAs with a pin-pitch of 0.8 mm or 1.0 mm. However, many of the queries I get from designers pertain to devices with a pitch less than 0.8 mm. Most of these queries are about 0.6-mm pitch, but some of them are about 0.5-mm and even 0.4-mm pitches. These devices are used commonly in handset products such as cell phones and PDAs. Just this week, I met a designer who completed a credit-card sized board that had seven BOAs on it!

Most smaller BOAs have relatively few pins--generally fewer than 200. The primary problem designing with these BOAs is to route out of the array requires very small features, making the design difficult to fabricate at a low cost and with high yields. But just when you thought that fine-pitch BOAs would remain with a small pin-count, get ready for some new processors with 600 pins on a 0.6-mm pitch.

Unfortunately, with the small devices, there is not much that can be done with fanouts to improve the route density. Nevertheless, this "not much" may be sufficient to help with your particular design. At this scale, there is only room to put a via-in-pad, so we need to look at methods for via placement that will enable additional traces in the route channels between the vias on the inner layers.

As a general note, the design rules for these very fine pin-pitch devices will have to be smaller than what is used with a standard FR-4 board. By using HDI, the traces can measure 0.75 mm and the micro-via pad can measure 0.25 mm with a 0.10-mm hole.

Shifting Via-In-Pad

FIGURE 1 illustrates the positive impact of shifting the via inside the pad just slightly to increase the center-to-center spacing to 0.595 mm. This will enable two traces between the vias, resulting in every other channel having two traces.

Another method, that applies to BOAs of all sizes, is to spread the perimeter vias away from the device that allows additional rows of ball pads to be escaped on fewer layers. I described it in the context of 0.8-mm devices, but it also can be used for 0.6 mm and below. This technique allows for an extra two rows of I/Os to be routed on the first signal layer...

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