On the road to 3D IC: ECTC showed fan-out wafer level packaging has many fans.

Author:Vardaman, E. Jan
Position:ON THE FOREFRONT
 
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ORLANDO IN MAY hosted the 64rd Electronics Components and Technology Conference (ECTC), where more than 1,000 attendees from 33 countries gathered to discuss recent developments in semiconductor packaging, assembly, materials and manufacturing.

While many presentations reported progress along the road to 3D IC manufacturing with through silicon vias (TSVs), the holy grail of stacking dies with different functions remained as elusive as Piglet--a shy creature who rarely makes an appearance in Disney's Magic Kingdom theme park. The need for 3D ICs remains constant, as companies ponder the cost of lithography at silicon technology nodes of lOnm and below.

Many research institutes such as Fraunhofer, IMEC, ITRI, NCAP, and others provided insight into process improvements that have taken place in the last year. Continued improvements in copper via reveal were reported, along with new materials, and equipment for wafer thinning, focusing on the debond step. Applied Materials announced its Ventura oxide and barrier coverage PVD system designed specifically for TSVs, providing better barrier and seed coverage on the walls, bottom and corners of copper vias, with improved speeds as a result of thinner films. Sachem and Solid State Equipment (SSEC) announced the release of Reveal Etch, a novel wet chemistry designed to enable a single-step silicon etch/TSV reveal process. SSEC worked with Sachem to develop this proprietary aqueous chemistry, which is residue-free and does not contain potassium. After years of dedicated R&D for this 2.5D/3D application, SSEC has integrated all the key components in a single tool--silicon thickness metrology for accurate endpointing determination, wet etch with a spin-etch chemistry to avoid using separate CMP equipment, a final etch with the chemistry to uniformly expose the TSVs, and wet cleaning. IBM provided information on use of a laser debond process in wafer thinning. IBM, Disco and Lasertec presented a TSV revealed process based on a metrology tool that uses IR reflectance to measure the silicon thickness remaining at the bottom of the TSV and backside surface of the wafer, coupled with a mechanical grinding and chemical mechanical polishing to expose the vias. Dow Electronic Materials discussed Pb-free solder plating developments for micro bumps.

A number of presentations focused on the potential for glass interposers, but whether the "glass" is half-full or half-empty was not clearly answered. Researchers...

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