CADENCE DEBUTS FRONT-END FOR SOC WITH HW/SW STRATEGY.

Cadence Design Systems, Inc. (NYSE:CDN), San Jose, Calif., has unveiled its first hardware and software (HW/SW) co- development products for managing the complexity and diverse nature of the system building blocks found in today's first- generation systems-on-a-chip (SOC).

At the heart of the company's strategy is a new SOC front-end for the functional specification and verification of reusable HW/SW virtual components starting at the system level. As a result, HW and SW architects can identify and solve system integration and performance issues early in the development cycle.

The first phase of Cadence's co-development product roadmap leverages the new Affirma(TM) HW/SW verifier for co-verification -- shipping in production this quarter -- and the virtual component co-design (VCC) products developed through Cadence's Felix Initiative. The VCC products are currently in pilot engagements with Felix partners and are now available on a limited basis through an early adopter program.

"Incremental technology improvements are not enough to solve the multi-faceted design challenges and huge methodology discontinuities facing designers," said Glenn Abood, vice president and general manager of Cadence's Design & Verification Business Unit. "We've focused our leading-edge R&D team on building the new front-end required for SOC, and today's announcement delivers the first installment of advanced technologies and methodologies."

Cadence Takes System-centric Approach

Cadence offers the only approach to system design that enables HW/SW co-development spanning from system specification and architectural evaluation to SOC integration. It raises the abstraction of the traditional design process from hardware implementation to "virtual" system prototyping. Using virtual components, system architects can rapidly explore HW/SW design trade-offs at the architectural level, and HW and SW designers can verify the functionality of HW and SW implementations within the context of the target system. By automating a specification-based flow, there is a higher degree of confidence and the risk is minimized between system designers (virtual component integrators) and their implementers and suppliers (virtual component providers).

High-performance Co-Verification

The Affirma HW/SW verifier lets designers achieve greater efficiency and apply the optimum level of verification during the refinement stages of the virtual system. The first release of the HW/SW verifier...

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